15 research outputs found
Three Essays on Computational Approaches to Economics
The three essays included in this dissertation are on three di?erent popular computational approaches that are widely applicable in economics. In Chapter 1, a state-space model is constructed which is linear in state variables and nonlinear in parameters. From the model, the time-varying level of natural interest rate is estimated using Kalman ?lter and Gibbs sampling algorithms. Chapter 2 proposes a new algorithm, called Implicit Particle Gibbs, to solve nonlinear state-space models. And Chapter 3 reviews recent development of deep learning and reinforcement learning algorithms and their applications in economics
Expressivity Enhancement with Efficient Quadratic Neurons for Convolutional Neural Networks
Convolutional neural networks (CNNs) have been successfully applied in a
range of fields such as image classification and object segmentation. To
improve their expressivity, various techniques, such as novel CNN
architectures, have been explored. However, the performance gain from such
techniques tends to diminish. To address this challenge, many researchers have
shifted their focus to increasing the non-linearity of neurons, the fundamental
building blocks of neural networks, to enhance the network expressivity.
Nevertheless, most of these approaches incur a large number of parameters and
thus formidable computation cost inevitably, impairing their efficiency to be
deployed in practice. In this work, an efficient quadratic neuron structure is
proposed to preserve the non-linearity with only negligible parameter and
computation cost overhead. The proposed quadratic neuron can maximize the
utilization of second-order computation information to improve the network
performance. The experimental results have demonstrated that the proposed
quadratic neuron can achieve a higher accuracy and a better computation
efficiency in classification tasks compared with both linear neurons and
non-linear neurons from previous works
SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement
Deep neural networks (DNNs) have successfully been applied in many fields in
the past decades. However, the increasing number of multiply-and-accumulate
(MAC) operations in DNNs prevents their application in resource-constrained and
resource-varying platforms, e.g., mobile phones and autonomous vehicles. In
such platforms, neural networks need to provide acceptable results quickly and
the accuracy of the results should be able to be enhanced dynamically according
to the computational resources available in the computing system. To address
these challenges, we propose a design framework called SteppingNet. SteppingNet
constructs a series of subnets whose accuracy is incrementally enhanced as more
MAC operations become available. Therefore, this design allows a trade-off
between accuracy and latency. In addition, the larger subnets in SteppingNet
are built upon smaller subnets, so that the results of the latter can directly
be reused in the former without recomputation. This property allows SteppingNet
to decide on-the-fly whether to enhance the inference accuracy by executing
further MAC operations. Experimental results demonstrate that SteppingNet
provides an effective incremental accuracy improvement and its inference
accuracy consistently outperforms the state-of-the-art work under the same
limit of computational resources.Comment: accepted by DATE2023 (Design, Automation and Test in Europe
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits
Given the stringent requirements of energy efficiency for Internet-of-Things
edge devices, approximate multipliers, as a basic component of many processors
and accelerators, have been constantly proposed and studied for decades,
especially in error-resilient applications. The computation error and energy
efficiency largely depend on how and where the approximation is introduced into
a design. Thus, this article aims to provide a comprehensive review of the
approximation techniques in multiplier designs ranging from algorithms and
architectures to circuits. We have implemented representative approximate
multiplier designs in each category to understand the impact of the design
techniques on accuracy and efficiency. The designs can then be effectively
deployed in high-level applications, such as machine learning, to gain energy
efficiency at the cost of slight accuracy loss.Comment: 38 pages, 37 figure
A Ferroelectric Compute-in-Memory Annealer for Combinatorial Optimization Problems
Computationally hard combinatorial optimization problems (COPs) are
ubiquitous in many applications, including logistical planning, resource
allocation, chip design, drug explorations, and more. Due to their critical
significance and the inability of conventional hardware in efficiently handling
scaled COPs, there is a growing interest in developing computing hardware
tailored specifically for COPs, including digital annealers, dynamical Ising
machines, and quantum/photonic systems. However, significant hurdles still
remain, such as the memory access issue, the system scalability and restricted
applicability to certain types of COPs, and VLSI-incompatibility, respectively.
Here, a ferroelectric field effect transistor (FeFET) based compute-in-memory
(CiM) annealer is proposed. After converting COPs into quadratic unconstrained
binary optimization (QUBO) formulations, a hardware-algorithm co-design is
conducted, yielding an energy-efficient, versatile, and scalable hardware for
COPs. To accelerate the core vector-matrix-vector (VMV) multiplication of QUBO
formulations, a FeFET based CiM array is exploited, which can accelerate the
intended operation in-situ due to its unique three-terminal structure. In
particular, a lossless compression technique is proposed to prune typically
sparse QUBO matrix to reduce hardware cost. Furthermore, a multi-epoch
simulated annealing (MESA) algorithm is proposed to replace conventional
simulated annealing for its faster convergence and better solution quality. The
effectiveness of the proposed techniques is validated through the utilization
of developed chip prototypes for successfully solving graph coloring problem,
indicating great promise of FeFET CiM annealer in solving general COPs.Comment: 39 pages, 12 figure
Emerging Technology Based Design of Primitives for Hardware Security
Hardware security concerns such as IP piracy and hardware Trojans have triggered research into circuit protection and malicious logic detection from various design perspectives. In this paper, emerging technologies are investigated by leveraging their unique properties for applications in the hardware security domain. Five example circuit structures including camouflaging gates, polymorphic gates, current/voltage based circuit protectors and current-based XOR logic are designed to prove the high efficiency of Silicon NanoWire FETs and Graphene SymFET in applications such as circuit protection and IP piracy prevention. Simulation results indicate that highly efficient and secure circuit structures can be achieved via the use of emerging technologies
Using Emerging Technologies For Hardware Security Beyond Pufs
We discuss how the unique I-V characteristics offered by emerging, post-CMOS transistors can be used to enhance hardware security. Different from most existing work that exploits emerging technologies for hardware security, we (i) focus on transistor characteristics that either do not exist in, or are difficult to duplicate with MOSFETs, and (ii) aim to move beyond hardware implementations of physically unclonable functions (PUFs) and random number generators (RNGs)